The present embodiments relate to electronic circuits and are more particularly directed to the simultaneous formation of multiple die on a wafer with common test points for each of the multiple die.
Integrated circuits are immensely prevalent in all aspects of contemporary electronic technology. Indeed, vast resources are expended in developing and implementing integrated circuit technology in order to supply demands imposed by the consuming marketplace. In this regard, the efficient production of integrated circuits is critical, and the present embodiments are directed at such efficiency. Particularly, the present embodiments improve the efficiency for testing integrated circuit during the manufacturing process and, therefore, improve the entire process of integrated circuit formation.
By way of introduction, the present state of the art for integrated circuit die fabrication includes one or more testing steps of each die so as to improve yield and to provide satisfactory devices to consumers. Testing, therefore, becomes part of the time required for fabricating and releasing integrated circuit devices. Accordingly, while the manner of testing must yield a sufficient number of acceptable devices, the time and cost for testing also must be minimized so as not to unduly drive up the price of each device, particularly given the nature of the present day competitive marketplace.
Integrated circuit testing in contemporary applications often involves the use of a probe card, such as are commercially available from the Cerprobe Corporation. The probe card typically includes a number of probe tips that extend in a tapered manner, where often the tapered tips are generally aligned in a single linear dimension so as to accommodate a set of bond pads located in the same single linear dimension on an integrated circuit die. The generally linear alignment of such bond pads is common in memory devices. However, with various other circuits, more complex constraints are imposed on the probe card due to attributes of the bond pads. For example, for devices other than memory, such as in the case of logic circuits or complex processors, often the bond pads are located on the integrated circuit die in various different locations across a two-dimensional space. As another example, the size of the bond pad as defined by its width and depth, and the distance, or “pitch”, between bond pads, are reduced as compared to older devices. As still another example, more complex integrated circuit devices typically include a much larger number of bond pads, even in a single dimension; thus, there is an attendant difficulty in providing a sufficient number of probe tips that can properly align with the large number of bond pads. In all events, therefore, these added complexities have given rise to the design of probe cards with a special geometry probe array in an effort to accommodate these more complex aspects. Such specialized probe cards, however, are considerably more expensive than their simpler counterparts and, indeed, the cost of such a card, particularly for devices with relatively small pitch sizes (e.g., 13 μm or less) may run in the tens of thousands of dollars. Further, these probe cards have a limited lifespan, which in part is exhausted according to the number of probe touches that occur in the use of the card, that is, the number of times each tip is used to touch a corresponding bond pad for testing. Note also that often two touches are required per bond pad, a first touch that is considered a “scrub” for essentially ensuring a clean contact to the pad and a second touch for the actual test to be applied via the probe tip. In any event, the probe card eventually deteriorates through numerous uses and, therefore, the above-described cost is repeatedly incurred as newer probe cards are warranted.
By way of further background, U.S. Pat. No. 5,444,366 (“the '366 patent”) issued on Aug. 22, 1995, entitled “Wafer Burn-In And Test System,” and is hereby incorporated herein by reference. The '366 patent describes a two-step process for forming a testing apparatus on top of devices that functionally are already completed on a semiconductor wafer. The first step applies two layers, an adhesive followed by a dielectric, and then both layers are patterned to make openings to previously-formed bond pads. The first step also requires the formation of two metal layers on top of the adhesive and dielectric, with a subsequent pattern and etch to form fuse link conductors, where at one end the fuse link contacts a bond bad and at the other end the fuse link contacts a via pad. The second step applies another dielectric covering the materials described above, followed by an etch and another metal layer that creates conductors that span in a columnar fashion across multiple devices and to a test point located in the non-patterned area of the wafer. Thereafter, the test point may be used for testing and burn-in procedures.
While the '366 patent may provide a useful testing mechanism for some devices, the present inventor has observed various of its drawbacks. For example, the testing architecture provided by the '366 patent comes at the cost of adding numerous additional layers to an integrated circuit that is already functionally complete, and those extra layers correspondingly require additional processing steps before testing can occur. In addition, presumably much if not all of the testing structure is required to be removed before the integrated circuit die is usually in a circuit package or the like, thereby possibly necessitating still additional manufacturing processes. In some contemporary applications, these additional actions would be too burdensome and, thus, render the approach of the '366 patent unusable for such applications.
In view of the above, there arises a need to address the drawbacks of the prior art as well as the complexities arising in contemporary probe card applications, and such needs are addressed by the preferred embodiments described below.